1. Field of the Invention
The present invention relates to an analog-digital converter, and more particularly, to an apparatus and method for adjusting a sampling clock phase in an analog-digital converter.
2. Discussion of the Related Art
Recently, as consumer demand for larger amount of information and higher picture quality has increased, digital televisions having such characteristics have been under development. The main function of such digital television is to simply display digital broadcast programs. However, as a multi-display device, the recently developed digital televisions also have other important functions, such as functioning as a monitor for displaying a personal computer (PC) screen and being connected to a conventional video equipment (e.g., a VCR, a DVD player, etc.) for display.
In order to eliminate distortion of such input video signals, many products adopting digital video interface methods, such as DVI interface or optical interface, are currently being developed and manufactured. However, due to various conventional video equipments that do not adopt the digital interface, or due to various video equipments adopting an analog interface, in display devices including digital televisions mostly receiving external inputs for display, analog-digital converters (ADCs) are used as important devices for converting analog signals to digital converters. When using such ADCs, deciding the phase of a sampling clock is an important factor for acquiring a digital video signal having no distortion. The importance of adjusting the phase of the sampling clock in an analog-digital converter (ADC) will now be described in detail with reference to the accompanying drawings.
FIGS. 1 to 3 illustrate sampling examples of an input signal in a general analog-digital converter. Referring to FIG. 1, the correspondence between the input signal and the clock of the ADC shows that a rising time of the clock may exist on a jitter region of the input signal. In this case, an unintended input signal value may be sampled. FIG. 2 illustrates an example of the input signal value being sampled at an ending point of the jitter region of the input signal. In this case, an instable input signal value may also be sampled. Finally, referring to FIG. 3, the rising time of the sampling clock is located in a stable section avoiding the jitter region of the input signal. In this case, since a stable input signal value is sampled, distortion of the data can be minimized.
As shown in FIGS. 1 and 3, by gradually modifying (or adjusting) the phase of the sampling clock, the ADC can compensate the phase. In order to adjust the sampling clock phase in the related art ADC, a method of calculating either an added value or a deviation value between a previous input pixel and a current input pixel for the entire input image. However, the method of calculating the added value of the deviation value between the previous input pixel and the current pixel for the entire input image is disadvantageous in that it may result in some limitations according to a pattern of the input image, and that the phase of the sampling clock may not be accurate. Thus, a problem of an instable conversion of an analog video signal to a digital video signal may occur in the related art ADC.